Reconfigurable Discrete Wavel.et Transform Architecture for Advanced Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform architecture is proposed to meet the diverse computing requirements of advanced multimedia systems. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable address generator handles flexible address generation for data I t0 access i n different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35pm IPJM CMOS process, and at 50MHz. it can achieve at most IOOM pixellsec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced multimedia systems.